AMS Digital Design Engineer Intern

Job description

<p></p>
<h1 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a" data-pm-slice="1 1 []">Digital RTL Design Engineer – Intern</h1>
<h2 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Role overview</h2>
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Astera Labs is seeking a motivated Digital RTL Design Intern to join our San Jose design team. This internship offers hands-on experience in digital logic design and RTL development for high-performance connectivity and networking ASICs.</p>
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">You will work closely with experienced architects and design engineers to translate design specifications into synthesizable RTL, develop and debug digital logic, and contribute to the design and integration of complex ASICs. You will collaborate with verification, synthesis, physical design, and other cross-functional teams throughout the ASIC development process.</p>
<h2 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Key responsibilities</h2>
<h3 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">RTL design and implementation</h3>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Develop and maintain synthesizable Verilog/SystemVerilog RTL for digital ASIC blocks and subsystems under the guidance of experienced engineers.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Translate design specifications into digital logic, including datapaths, control logic, finite state machines, counters, register interfaces, and other functional blocks.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Implement, modify, and integrate RTL modules following established design and coding guidelines.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Participate in RTL code reviews and contribute to design quality, readability, reusability, and maintainability.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Debug RTL functionality and assist with resolving design and integration issues.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Learn and apply digital design best practices for performance, power, and area optimization.</p>
</li>
</ul>
<h3 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Functional verification and debugging</h3>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Run RTL simulations and debug functional issues using waveforms, simulation logs, and debugging tools.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Work with design verification engineers to understand design requirements and validate RTL functionality.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Assist with identifying corner cases and resolving functional issues discovered during simulation.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Support RTL lint checks and other design-quality checks.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Develop familiarity with verification methodologies, SystemVerilog assertions, and regression-based testing.</p>
</li>
</ul>
<h3 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">ASIC design flow and implementation support</h3>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Gain exposure to the ASIC development flow, including synthesis, timing analysis, and physical design.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Review basic synthesis and timing reports to understand how RTL coding decisions affect hardware implementation.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Assist with investigating timing or synthesis issues in collaboration with experienced design engineers.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Support RTL integration and design-readiness activities throughout the development cycle.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Learn industry-standard EDA tools and methodologies used in digital ASIC design.</p>
</li>
</ul>
<h3 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Cross-functional collaboration</h3>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Collaborate with design verification, synthesis, physical design, DFT, and other engineering teams to support ASIC development.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Participate in technical discussions, design reviews, and project meetings.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Document design functionality, debugging results, and technical issues.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Gain exposure to tapeout, silicon bring-up, and post-silicon debugging as project opportunities arise.</p>
</li>
</ul>
<h2 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Basic qualifications</h2>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Fundamental understanding of digital logic design, including combinational and sequential logic, flip-flops, finite state machines, and basic datapaths.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Basic knowledge of Verilog or SystemVerilog through coursework, academic projects, research, or internships.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Familiarity with digital design concepts such as clocks, resets, counters, FIFOs, and register-based interfaces.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Basic understanding of digital simulation and hardware design principles.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Strong analytical, problem-solving, and debugging skills.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Eagerness to learn new technologies and work on challenging engineering problems.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Good communication skills and the ability to work effectively in a collaborative team environment.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Ability and willingness to work onsite in San Jose, California.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">No prior industry experience is required; relevant coursework, academic projects, research, and internships will be considered.</p>
</li>
</ul>
<h2 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Preferred qualifications</h2>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Experience developing Verilog/SystemVerilog RTL through academic projects, FPGA development, research, or internships.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Familiarity with RTL simulation and waveform-debugging tools.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Exposure to digital ASIC or FPGA design flows.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Basic understanding of synthesis, static timing analysis, or physical design concepts.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Familiarity with Python, Tcl, Perl, Shell, or other scripting languages.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Exposure to high-speed interfaces or communication protocols such as PCI Express, Ethernet, AMBA, CXL, or other networking and interconnect technologies.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Familiarity with verification concepts such as SystemVerilog assertions, UVM, functional coverage, or formal verification.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Interest in high-performance ASICs, networking, data-center infrastructure, or AI and cloud computing.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Demonstrated ability to learn new technical concepts and apply them to practical engineering problems.</p>
</li>
</ul>
<h2 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Internship experience and compensation</h2>
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges form $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.</p>
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