AMS Design Verification Engineer Intern

Job description

<p></p>
<h1 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a" data-pm-slice="1 1 []">Design Verification Engineer – Intern</h1>
<h2 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Role overview</h2>
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Astera Labs is seeking a motivated Digital Design Verification Intern to join our San Jose design team. This internship offers hands-on experience in functional verification of high-performance connectivity and networking ASICs.</p>
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">You will work with experienced design and verification engineers to understand design specifications, develop and execute verification tests, debug simulation failures, and help assess the functionality and reliability of complex digital designs. You will collaborate with RTL design, architecture, and other engineering teams throughout the ASIC development process.</p>
<h2 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Key responsibilities</h2>
<h3 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Functional verification and test development</h3>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Assist in developing and executing simulation-based test plans for digital ASIC blocks and subsystems.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Develop and maintain test cases using SystemVerilog and other verification languages under the guidance of experienced engineers.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Help identify functional scenarios, corner cases, and potential design issues from design specifications.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Run simulations and analyze results to verify that RTL behavior meets design requirements.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Contribute to test quality, verification efficiency, and functional coverage improvements.</p>
</li>
</ul>
<h3 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Simulation debugging and design quality</h3>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Debug simulation failures using waveforms, simulation logs, and debugging tools.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Work with RTL design engineers to investigate functional issues and help identify root causes.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Assist with regression testing and track verification results.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Learn and apply verification best practices, including assertions, functional coverage, and systematic debugging.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Help maintain verification environments and test documentation.</p>
</li>
</ul>
<h3 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Verification methodology and automation</h3>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Gain exposure to SystemVerilog-based verification environments and object-oriented programming concepts.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Learn Universal Verification Methodology (UVM) and contribute to existing testbenches as appropriate.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Assist with reusable verification components, test sequences, and checkers.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Use Python, Tcl, Shell, or similar scripting languages to automate repetitive verification tasks.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Participate in code reviews and contribute to verification-code quality and maintainability.</p>
</li>
</ul>
<h3 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Cross-functional collaboration</h3>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Collaborate with RTL design, architecture, and verification engineers to understand design functionality and verification requirements.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Participate in design reviews, verification planning, and technical discussions.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Document test scenarios, debugging results, and verification progress.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Gain exposure to ASIC development milestones, including block integration, regression signoff, tapeout, and post-silicon validation.</p>
</li>
</ul>
<h2 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Basic qualifications</h2>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Fundamental understanding of digital logic design, including combinational and sequential logic, flip-flops, finite state machines, and basic datapaths.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Basic programming knowledge in at least one language such as C, C++, Python, or SystemVerilog.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Basic understanding of hardware design concepts, including clocks, resets, registers, and state machines.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Familiarity with digital simulation or hardware design through coursework, academic projects, research, or internships.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Strong analytical, problem-solving, and debugging skills.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Willingness to learn new verification tools, methodologies, and technologies.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Good communication skills and the ability to work effectively in a collaborative team environment.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Ability and willingness to work onsite in San Jose, California.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">No prior industry experience is required; relevant coursework, academic projects, research, and internships will be considered.</p>
</li>
</ul>
<h2 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Preferred qualifications</h2>
<ul class="wnfdntj">
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Experience with Verilog or SystemVerilog through coursework, academic projects, or internships.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Exposure to RTL simulation tools and waveform debugging.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Familiarity with digital-design verification concepts, testbench development, or functional coverage.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Basic knowledge of object-oriented programming or SystemVerilog assertions.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Exposure to UVM or other constrained-random verification methodologies.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Experience with Python, Tcl, Perl, Shell, or other scripting languages for automation.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Familiarity with ASIC or FPGA development flows.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Exposure to high-speed interfaces or protocols such as PCI Express, Ethernet, AMBA, CXL, NVMe, or other networking and interconnect technologies.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Interest in high-performance ASICs, networking, data-center infrastructure, AI accelerators, or cloud computing.</p>
</li>
<li class="wnfdnte _1ibi0s35c">
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">Demonstrated ability to learn complex technical concepts and apply them to practical engineering problems.</p>
</li>
</ul>
<h2 class="wnfdntn wnfdntm _1ibi0s35e _1ibi0s36a">Internship experience and compensation</h2>
<p class="wnfdnt10 _1ibi0s3fd _1ibi0s3ce _1ibi0s3eg">This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges form $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.</p>
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