Signal Integrity Solutions Architect Intern

Job description

<p><strong><span data-contrast="auto">Signal Integrity Solutions Architect Intern</span></strong><span data-ccp-props="{}"> </span></p>
<p><span data-contrast="auto">As a Signal Integrity Intern on the Solutions Architecture team, you will model system-level channels across a wide range of compute and switch architectures to determine what is feasible for next-generation AI infrastructure. You will uncover the constraints, bottlenecks, and limitations that shape rack-scale designs, and turn those findings into clear guidance on what is possible.</span><span data-ccp-props="{}"> </span></p>
<p><span data-contrast="auto">Your analyses will directly influence Astera Labs' product roadmap and feature set, ensuring our connectivity solutions meet system-level signal integrity goals as AI data rates keep climbing. You will work alongside solutions architects, hardware engineers, and silicon teams at a hyper-growth company whose purpose-built connectivity powers the world's leading AI platforms.</span><span data-ccp-props="{}"> </span></p>
<p><strong><span data-contrast="auto">Responsibilities</span></strong><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><strong><span data-contrast="auto">System Channel Modeling</span></strong><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="auto">Build and run system-level channel models for a variety of compute and switch architectures</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2"><span data-contrast="auto">Evaluate the feasibility of next-generation architectures across PCIe, Ethernet, and UALink interconnects</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2"><span data-contrast="auto">Identify constraints, bottlenecks, and limitations in end-to-end channel performance</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1"><strong><span data-contrast="auto">Sensitivity and Trade-off Analysis</span></strong><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="auto">Perform sensitivity analyses to understand interaction effects between channel parameters</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2"><span data-contrast="auto">Determine the main drivers of channel performance and quantify their impact on margin</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2"><span data-contrast="auto">Explore design trade-offs to define what is achievable at the system level</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><strong><span data-contrast="auto">Roadmap and Cross-Functional Influence</span></strong><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="auto">Translate modeling results into system-driven inputs that shape product roadmaps and feature sets</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="2"><span data-contrast="auto">Partner with solutions architecture, hardware engineering, and silicon engineering teams to align on signal integrity goals</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="2"><span data-contrast="auto">Document findings and present results to technical teams and stakeholders in clear, concise formats</span><span data-ccp-props="{}"> </span></li>
</ul>
<p><strong><span data-contrast="auto">Basic Qualifications</span></strong><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="13" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, or a related technical field</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="13" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Coursework or project experience in signal integrity, transmission lines, electromagnetics, or high-speed digital design</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="13" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Basic understanding of high-speed serial link concepts such as insertion loss, return loss, crosstalk, and equalization</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="13" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Familiarity with the physical layer of high-speed interconnect standards such as PCIe or Ethernet</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="13" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Proficiency with a scripting or analysis tool such as Python or MATLAB for data processing and modeling</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="13" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="auto">Strong written and verbal communication skills, with the ability to present technical findings clearly</span><span data-ccp-props="{}"> </span></li>
</ul>
<p><strong><span data-contrast="auto">Preferred Qualifications</span></strong><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Currently pursuing a Master's or PhD in Electrical Engineering or a related field</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Hands-on experience with channel simulation tools (e.g., Keysight ADS, Ansys HFSS, or similar) or S-parameter analysis</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Familiarity with PCIe Gen 6 or Gen 7, high-speed Ethernet, or UALink</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Experience with statistical or design-of-experiments methods for sensitivity analysis</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Curiosity and initiative to learn quickly in a fast-paced, collaborative environment</span><span data-ccp-props="{}"> </span></li>
</ul>
<p><span data-ccp-props="{}"></span></p>
<h2>Internship experience and compensation</h2>
<p>This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges from $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.</p>
<h2>Equal opportunity</h2>
<p>Astera Labs is an equal opportunity employer committed to fostering a diverse and inclusive workplace. We encourage anyone with relevant experience to apply.</p>
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