Design Verification Engineer Intern

Job description

<p> </p>
<h1 class="wnfdnti _1ibi0s33y _1ibi0s34u" data-pm-slice="1 1 []">Design Verification Engineer Intern</h1>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Astera Labs · San Jose, CA · Internship · On-site</strong></p>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">About Astera Labs</h2>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Astera Labs builds connectivity solutions that help power modern AI infrastructure. Our Hardware Engineering teams design and validate high-performance products that connect processors, accelerators, memory, and network fabrics.</p>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">The opportunity</h2>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Join the Design Verification team and help validate digital designs before and after silicon. You’ll learn the team’s verification flow, develop and run tests, analyze simulations and waveforms, and contribute to the regressions and coverage that help ensure products behave as intended.</p>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">This internship is designed for someone who enjoys understanding how a design should work, creating experiments that exercise it, and investigating the evidence when results differ from expectations. You’ll work with experienced verification and design engineers on a meaningful project with visible product impact, while building practical skills in digital design verification and semiconductor development.</p>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">What you’ll do</h2>
<ul class="wnfdntf">
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Learn the product domain, assigned project, verification environment, test flow, and tools needed to contribute effectively.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Read specifications and design documentation to understand functionality, interfaces, corner cases, and verification requirements.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Develop or extend simulation tests and verification components under engineering guidance, using SystemVerilog, UVM-style methodologies, Python, or related tools.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Run simulations and regressions in a Linux environment using the team’s submission scripts, workspace setup, and test definitions.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Analyze test logs, errors, assertions, and simulation output to identify failures and determine whether the issue is in the test, environment, design, or infrastructure.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Use waveform-debug tools such as Verdi or DVE to inspect signal behavior and explain the sequence of events leading to a failure.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Add or update tests, test definitions, regression lists, manifests, and supporting scripts to improve coverage and confidence in the design.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Review coverage results and help identify meaningful gaps in functional or code coverage.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Collaborate with design, firmware, validation, and other engineering teams to communicate findings, reproduce issues, and track corrective actions.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Participate in code reviews, technical discussions, issue tracking, documentation, and project planning.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Take ownership of an assigned verification project, deliver the work in a usable state, and explain what was verified and how it supported the product flow.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Present your project, results, and key learnings at the end of the internship.</p>
</li>
</ul>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">What you bring</h2>
<ul class="wnfdntf">
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, or a related field.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Foundational understanding of digital logic, computer architecture, RTL, hardware interfaces, or software development.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Programming experience in one or more of SystemVerilog, Verilog, Python, C, C++, or a comparable language.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Curiosity about how complex digital designs work and a methodical approach to testing assumptions and debugging failures.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Comfort learning in a Linux environment and working with source control, command-line tools, and technical documentation.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Ability to organize priorities, ask focused questions, take ownership of deliverables, and communicate progress and blockers clearly.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Persistence, learning agility, and a collaborative mindset in an environment where verification work requires iteration and investigation.</p>
</li>
</ul>
<h3 class="wnfdnti _1ibi0s33y _1ibi0s34u">Helpful experience</h3>
<ul class="wnfdntf">
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">SystemVerilog, UVM, constrained-random testing, assertions, scoreboards, monitors, drivers, or functional coverage.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">RTL design or verification using Verilog, SystemVerilog, or similar hardware description languages.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Simulation and waveform-debug tools such as VCS, Verdi, DVE, or related EDA tools.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Python or shell scripting for test generation, regression management, log parsing, or data analysis.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Familiarity with simulation regressions, test manifests, coverage databases, or CI/test infrastructure.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Exposure to PCIe, CXL, Ethernet, SERDES, memory systems, SoC design, or other high-speed connectivity technologies.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Git, Jira, Confluence, or similar tools for collaborative engineering workflows.</p>
</li>
</ul>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">Internship experience and compensation</h2>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges from $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.</p>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">Equal opportunity</h2>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Astera Labs is committed to providing equal employment opportunities to all applicants and employees. We value diverse perspectives and consider qualified candidates without regard to legally protected characteristics.</p>
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