Design Engineering Intern (CCE2)

Job description

<p></p>
<h1 class="wnfdnti _1ibi0s33y _1ibi0s34u" data-pm-slice="1 1 []">Design Engineer Intern (CCE2)</h1>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea"><strong>Astera Labs · San Jose, CA · Internship · On-site</strong></p>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">About Astera Labs</h2>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Astera Labs builds connectivity solutions that help power modern AI infrastructure. Compute Connectivity Engineering 2 (CCE2) develops complex silicon and connectivity products for high-performance systems, including technologies such as PCIe, CXL, and UALink.</p>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">The opportunity</h2>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Join the CCE2 Design Engineering team and gain hands-on experience developing digital logic for advanced connectivity ASICs. You’ll work at the intersection of architecture, RTL, simulation, synthesis, verification, physical design, DFT, and firmware to help turn product requirements into robust, implementable hardware.</p>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">This internship is designed for someone who enjoys understanding how a system should work, expressing that behavior in RTL, and debugging the difference between intended and observed results. You’ll work with experienced design engineers on a meaningful project involving a block, subsystem, interface, datapath, control path, or reusable design infrastructure.</p>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">What you’ll do</h2>
<ul class="wnfdntf">
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Learn the product architecture, microarchitecture, design methodology, development environment, tools, and project workflow needed to contribute effectively.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Read architecture, interface, microarchitecture, and product-requirement documentation and translate requirements into clear design behavior.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Design, implement, modify, and document synthesizable RTL in Verilog or SystemVerilog under engineering guidance.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Contribute to datapaths, control logic, state machines, register interfaces, configuration and status logic, error handling, arbitration, buffering, or other digital design functions.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Work with interface and connectivity logic for technologies such as PCIe, CXL, UALink, Ethernet, SERDES, or related high-speed systems as appropriate for the project.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Develop or update design specifications, block diagrams, interface definitions, register descriptions, timing assumptions, and design documentation.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Run simulations and use waveforms, logs, assertions, and regression results to debug RTL behavior and verify design changes.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Support lint, CDC/RDC, synthesis, formal, low-power, or related design-quality checks and investigate issues with guidance from experienced engineers.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Collaborate with Design Verification to make interfaces and behavior testable, review coverage or failures, and resolve issues found during verification.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Work with physical design, DFT, emulation, firmware, validation, and architecture teams to understand constraints, handoffs, and implementation impact.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Contribute to scripts, configuration, test collateral, reports, code reviews, issue tracking, and design-flow improvements.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Deliver assigned design work in a reproducible, reviewable, and well-documented state and present your project, results, and key learnings at the end of the internship.</p>
</li>
</ul>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">What you bring</h2>
<ul class="wnfdntf">
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, or a related field.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Foundational understanding of digital logic, RTL, computer architecture, finite-state machines, computer arithmetic, or hardware interfaces.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Experience with Verilog, SystemVerilog, VHDL, C/C++, Python, or another language used in digital design and automation.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Curiosity about how complex silicon designs work and a methodical approach to translating requirements into testable, maintainable logic.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Comfort learning in Linux and working with command-line tools, source control, technical specifications, logs, waveforms, and development scripts.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Ability to ask focused questions, communicate assumptions and blockers, accept design feedback, and follow through on commitments.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Ownership, learning agility, persistence, and a collaborative mindset in a fast-moving silicon-development environment.</p>
</li>
</ul>
<h3 class="wnfdnti _1ibi0s33y _1ibi0s34u">Helpful experience</h3>
<ul class="wnfdntf">
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">RTL design, simulation, assertions, lint, CDC/RDC, synthesis, formal analysis, or design-for-test concepts.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">SystemVerilog interfaces, parameterized modules, FIFOs, arbiters, pipelines, state machines, register maps, or bus protocols.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">PCIe, CXL, UALink, Ethernet, SERDES, retimers, switches, memory systems, SoC design, or other high-speed connectivity technologies.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">EDA tools such as VCS, Verdi, DVE, Design Compiler, Fusion Compiler, or comparable tools.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Python, Tcl, Bash, or other scripting for automation, report parsing, regression support, or data analysis.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Emulation, FPGA prototyping, gate-level simulation, timing constraints, power-aware design, or hardware bring-up.</p>
</li>
<li class="wnfdnte _1ibi0s33w">
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Git, Bitbucket, Jira, Confluence, Slurm, or similar collaborative engineering workflows.</p>
</li>
</ul>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">Internship experience and compensation</h2>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges from $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.</p>
<h2 class="wnfdnti _1ibi0s33y _1ibi0s34u">Equal opportunity</h2>
<p class="wnfdntu _1ibi0s3f5 _1ibi0s3ce _1ibi0s3ea">Astera Labs is committed to providing equal employment opportunities to all applicants and employees. We value diverse perspectives and consider qualified candidates without regard to legally protected characteristics.</p>
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